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Espressif Systems /ESP32-C2 /UART0 /CONF0

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Interpret as CONF0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PARITY)PARITY 0 (PARITY_EN)PARITY_EN 0BIT_NUM 0STOP_BIT_NUM 0 (SW_RTS)SW_RTS 0 (SW_DTR)SW_DTR 0 (TXD_BRK)TXD_BRK 0 (IRDA_DPLX)IRDA_DPLX 0 (IRDA_TX_EN)IRDA_TX_EN 0 (IRDA_WCTL)IRDA_WCTL 0 (IRDA_TX_INV)IRDA_TX_INV 0 (IRDA_RX_INV)IRDA_RX_INV 0 (LOOPBACK)LOOPBACK 0 (TX_FLOW_EN)TX_FLOW_EN 0 (IRDA_EN)IRDA_EN 0 (RXFIFO_RST)RXFIFO_RST 0 (TXFIFO_RST)TXFIFO_RST 0 (RXD_INV)RXD_INV 0 (CTS_INV)CTS_INV 0 (DSR_INV)DSR_INV 0 (TXD_INV)TXD_INV 0 (RTS_INV)RTS_INV 0 (DTR_INV)DTR_INV 0 (CLK_EN)CLK_EN 0 (ERR_WR_MASK)ERR_WR_MASK 0 (AUTOBAUD_EN)AUTOBAUD_EN 0 (MEM_CLK_EN)MEM_CLK_EN

Description

a

Fields

PARITY

This register is used to configure the parity check mode.
PARITY_EN

Set this bit to enable uart parity check.
BIT_NUM

This register is used to set the length of data.
STOP_BIT_NUM

This register is used to set the length of stop bit.
SW_RTS

This register is used to configure the software rts signal which is used in software flow control.
SW_DTR

This register is used to configure the software dtr signal which is used in software flow control.
TXD_BRK

Set this bit to enbale transmitter to send NULL when the process of sending data is done.
IRDA_DPLX

Set this bit to enable IrDA loopback mode.
IRDA_TX_EN

This is the start enable bit for IrDA transmitter.
IRDA_WCTL

1’h1: The IrDA transmitter’s 11th bit is the same as 10th bit. 1’h0: Set IrDA transmitter’s 11th bit to 0.
IRDA_TX_INV

Set this bit to invert the level of IrDA transmitter.
IRDA_RX_INV

Set this bit to invert the level of IrDA receiver.
LOOPBACK

Set this bit to enable uart loopback test mode.
TX_FLOW_EN

Set this bit to enable flow control function for transmitter.
IRDA_EN

Set this bit to enable IrDA protocol.
RXFIFO_RST

Set this bit to reset the uart receive-FIFO.
TXFIFO_RST

Set this bit to reset the uart transmit-FIFO.
RXD_INV

Set this bit to inverse the level value of uart rxd signal.
CTS_INV

Set this bit to inverse the level value of uart cts signal.
DSR_INV

Set this bit to inverse the level value of uart dsr signal.
TXD_INV

Set this bit to inverse the level value of uart txd signal.
RTS_INV

Set this bit to inverse the level value of uart rts signal.
DTR_INV

Set this bit to inverse the level value of uart dtr signal.
CLK_EN

1’h1: Force clock on for register. 1’h0: Support clock only when application writes registers.
ERR_WR_MASK

1’h1: Receiver stops storing data into FIFO when data is wrong. 1’h0: Receiver stores the data even if the received data is wrong.
AUTOBAUD_EN

This is the enable bit for detecting baudrate.
MEM_CLK_EN

UART memory clock gate enable signal.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd